1. Field of the Invention
The present invention relates to a method and apparatus for minimizing the effects of defects in an integrated circuit chip. More specifically, the present invention implements redundancy in highly parallel memory structures.
2. Art Background
It is quite common for a fast central processor unit to feature parallel data paths such as a 32-bit or a 64-bit bus for transferring data into and out of its memory storage. Likewise, most memory storage comprises semiconductor memories organized in rectangular arrays of rows and columns on very-large-scale integrated (VLSI) circuits. The intersection of one row and one column results in a storage element called a "cell". Each cell is capable of storing a binary bit of data. To write data into, and to read data from, a row or column of cells, an address is assigned to each row or column of cells. Access to the address is provided by a binary-coded address presented as input to address decoders that select a row or column for a write or read operation. As semiconductor memories become more and more dense, the arrays of cells become more and more susceptible to the presence of defects which could impede or corrupt the flow of data through any of the desired paths.
Defects in semiconductor memories occur during the fabrication, packaging and field operation of an integrated circuit. Under the rubric of defects, one may include wafer defects, oxide defects, metallization defects, interconnect defects, contamination defects, unintended or missing connections, missing or extra contacts and others. To avoid unnecessarily confusing the presentation of the invention, an "open" defect refers to a defect affecting the data path for one bit of data, while a "short" defect refers to a defect affecting the paths of more than one bit of data.
On-chip redundancy is the construction of redundant elements on an integrated chip to bypass the data paths affected by the defects while preserving the original addresses of the affected data paths. Redundancy is also used to overcome the presence of defects in VLSI circuits such as memory storage. Redundancy is also employed to improve the reliability of computers in sensitive applications (e.g., the backup computers on a space shuttle), or to reduce the down time of the systems (e.g., a redundant computer for monitoring traffic lights). As a result, on-chip redundancy not only improves the yield but also the reliability of integrated circuits.
In the past, on-chip redundancy was implemented with latches or laser zappable fuses located on each column or row of data path. Latches are volatile and require that the information identifying the cells affected by defects be stored external to the semiconductor memory, for example, on a disk, so that when power is turned on, the entire system does not have to be retested for defects.
Laser zappable fuses are physically implemented in CMOS circuits in one of two ways. If the fuse is "normally closed," it is usually made with a polysilicon fuse which can be opened by selective laser zapping. If the fuse is "normally open," it is usually made with a NMOS or a PMOS transistor whose gate voltage is controlled by "normally closed" laser zappable fuses.
The use of latches or laser zappable fuses on each column or row of data path imposes technology constraints. In particular, to avoid damage to surrounding circuitry when a fuse is "zapped," considerable space must be allowed between each fuse and other fuses or other unrelated circuitry. The additional area required for the fuses is generally contradictory with the tight spacing requirements inherent in memory arrays. As applicable to wide-word computing such as the popular use of 32-bit or 64-bit data paths, a number of additional problems arise. A single redundant set of arrays cannot compensate for a short defect between arrays belonging to two adjacent sets. Therefore, at least two sets would be needed to correct such defects. Additionally, data transmissions along the redundant path can suffer a speed penalty due to the extra line length and the incidence of higher parasitic capacitance. In some instances, the input and output data path may be tripled in length for a wide-word computing device. Variable delays from data paths are highly undersirable in high-performance memory storage, as they force the performance of an entire memory array to be no better than that of the extended length path's performance. In addition, laser zappable fuses are irreversible, i.e. once a fuse is blown, it cannot be changed. Finally, fuses must be laid out integrally to each set so as to be able to selectively disconnect sets in which defects exist. (See, "A 50 ns 16 Mb DRAM with a 10 ns Data Rate", Digest of Technical Papers, IEEE International Solid-State Circuits Conference, February 1990, pp 232-233.)